1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, it relates to a liquid crystal display (LCD) device including a polycrystalline silicon thin film transistor (p-Si TFT) and a method of fabricating the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are being developed as the next generation of display devices because of their advantageous characteristics of light weight, thin profile, and low power consumption. In general, an LCD device is a non-emissive display device that displays images by making use of a refractive index difference through utilizing optical anisotropy properties of liquid crystal molecules interposed between an array substrate and a color filter substrate. When an electric field is applied to liquid crystal molecules, the liquid crystal molecules are realigned. As a result, light transmittance of the liquid crystal molecules is changed according to a new alignment direction of the realigned liquid crystal molecules.
Recently, active matrix liquid crystal display (AM LCD) devices having thin film transistors (TFTs) and pixel electrodes arranged in matrix has been widely researched because of their superior resolution and capability to smoothly display moving images. The TFTs using hydrogenated amorphous silicon (a-Si:H) may be fabricated under a relatively low temperature. In hydrogenated amorphous silicon, however, since atoms are randomly arranged, weak bonds and dangling bonds exist. Accordingly, when light is irradiated or an electric field is applied, the hydrogenated amorphous silicon has a quasi-static state and this quasi-static state may deteriorate the stability of the TFT. Furthermore, the TFT using hydrogenated amorphous silicon may not be used for a driving circuit because of its relatively low mobility within a range of about 0.1 cm2/V·sec to about 1.0 cm2/V·sec.
To overcome these drawbacks of the TFT using hydrogenated amorphous silicon, a TFT using polycrystalline silicon (p-Si) has been suggested for an LCD device. Polycrystalline silicon has a mobility that is one or two hundred times higher than that of hydrogenated amorphous silicon and a faster response time than that of hydrogenated amorphous silicon. Moreover, polycrystalline silicon is more stable against light, heat and electric field than hydrogenated amorphous silicon. Accordingly, the TFT including polycrystalline silicon may be used for a driving circuit of an LCD device and fabricated on a single substrate having a pixel TFT.
FIG. 1 is a schematic plan view of an array substrate including a driving circuit using polycrystalline silicon according to the related art. In FIG. 1, a substrate 1 has a pixel portion 3 at its central portion and a driving portion 5 at a periphery of the pixel portion 3. The driving portion 5 includes a gate driving unit 5a and a data driving unit 5b. A plurality of gate lines 7 connected to the gate driving unit 5a and a plurality of data lines 9 connected to the data driving unit 5b are disposed in the pixel portion 3. The plurality of gate lines 7 cross the plurality of data lines 9 to define a pixel region “P” and a pixel electrode 10 is formed in the pixel region “P.” A thin film transistor (TFT) “T” in the pixel region “P” is connected to the gate line 7, the data line 9 and the pixel electrode 10. In addition, the gate driving unit 5a and the data driving unit 5b are connected to external signal input terminals 12. The gate driving unit 5a and the data driving unit 5b generate control signals, a gate signal and a data signal using external signals from the external signal input terminals 12 and supply the generated signals to the pixel portion 3 through the gate line 7 and the data line 9. The gate driving unit 5a and the data driving unit 5b may include TFTs using a complementary metal-oxide-semiconductor (CMOS) logic for quicker treatment of signals. Generally, a CMOS logic is used for driving TFTs where a fast signal processing is required. A p-type TFT using holes as carriers and a n-type TFT using electrons as a carrier are used for the CMOS logic. The p-type TFT and the n-type TFT are complementarily controlled.
FIG. 2A is a schematic cross-sectional view showing a switching element of a pixel portion according to the related art and FIG. 2B is a schematic cross-sectional view showing CMOS switching elements of a driving portion according to the related art. In FIG. 2A, a buffer layer 25 of an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiO2), is formed on a substrate 20. A first semiconductor layer 30 is formed on the buffer layer 25 and a gate insulating layer 45 is formed on the semiconductor layer 30. In addition, a first gate electrode 50 is formed on the gate insulating layer 45 over the first semiconductor layer 30 and an interlayer insulating layer 70 is formed on the first gate electrode 50. The interlayer insulating layer 70 has a first set of contact holes 73a and 73b exposing the first semiconductor layer 30. First source and drain electrodes 80a and 80b are formed on the interlayer insulating layer 70. The first source and drain electrodes 80a and 80b are connected to the first semiconductor layer 70 through the first set of contact holes 73a and 73b. A passivation layer 90 is formed on the first source and drain electrodes 80a and 80b. The passivation layer 90 has a first drain contact hole 95 exposing the first drain electrode 80b. A pixel electrode 97 is formed on the passivation layer 90 and connected to the first drain electrode 80b through the first drain contact hole 80.
The first semiconductor layer 30 includes a first active region 30a corresponding to the first gate electrode 50, a first ohmic contact region 30c at both sides of the first active region 30a and a first lightly doped drain (LDD) region 30b interposed between the first active region 30a and the first ohmic contact region 30c. The first ohmic contact region 30c is connected to the first source and drain electrodes 80a and 80b. The first ohmic contact region 30c is doped with n-type impurities of a high concentration (n+), while the first LDD region 30b is doped with n-type impurities of a low concentration (n−). The first LDD region reduces leakage current by alleviating an electric field between the first gate electrode 50 and the first ohmic contact region 30c of the first semiconductor layer 30. Accordingly, a switching element of a pixel portion may be formed of an n-type LDD polycrystalline silicon TFT “I.”
In FIG. 2B, CMOS switching elements of a driving portion include an n-type LDD polycrystalline silicon TFT “II” and a p-type polycrystalline silicon TFT “III.” The buffer layer 25 is formed on the substrate 20. A second semiconductor layer 35 and a third semiconductor layer 40 spaced apart from each other are formed on the buffer layer 25. The gate insulating layer 45 is formed on the second semiconductor layer 35 and the third semiconductor layer 40. In addition, second and third gate electrodes 55 and 60 are formed on the gate insulating layer 45 over the second and third semiconductor layers 35 and 40, respectively. The interlayer insulating layer 70 is formed on the second and third gate electrodes 55 and 60. The interlayer insulating layer 70 has second set of contact holes 75a and 75b exposing the second semiconductor layer 35, and third set of contact holes 77a and 77b exposing the third semiconductor layer 40. Second source and drain electrodes 83a and 83b and third source and drain electrodes 87a and 87b are formed on the interlayer insulating layer 70. The second source and drain electrodes 83a and 83b are connected to the second semiconductor layer 35 through the second set of contact holes 75a and 75b, respectively, and the third source and drain electrodes 87a and 87b are connected to the third semiconductor layer 40 through the third set of contact holes 77a and 77b, respectively.
The second semiconductor layer 35 includes a second active region 35a corresponding to the second gate electrode 55, a second ohmic contact region 35c at both sides of the second active region 35a and a second LDD region 35b interposed between the second active region 35a and the second ohmic contact region 35c. The second ohmic contact region 35c is connected to the second source and drain electrodes 83a and 83b. The second ohmic contact region 35c is doped with n-type impurities of a high concentration (n+), while the second LDD region 35b is doped with n-type impurities of a low concentration (n−). In addition, the third semiconductor layer 40 includes a third active region 40a corresponding to the third gate electrode 60 and a third ohmic contact region 40c at both sides of the third active region 40a. The third ohmic contact region 40c is doped with p-type impurities of a high concentration (p+). Since holes are used as carriers in p-type elements, no leakage current occurs. Thus, an LDD region may be omitted in p-type elements. Accordingly, CMOS switching elements of a driving portion may be formed of an n-type LDD polycrystalline silicon TFT “II” and a p-type polycrystalline silicon TFT “III.”
FIGS. 3A to 3F are schematic cross-sectional views showing a process of fabricating a switching element of a pixel portion according to the related art, and FIGS. 4A to 4F are schematic cross-sectional views showing a process of fabricating CMOS switching elements of a driving portion according to the related art.
In FIGS. 3A and 4A, a buffer layer 25 is formed on a substrate 20 by depositing an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiO2). After amorphous silicon (a-Si) is deposited on the buffer layer 25, the deposited amorphous silicon may be dehydrogenated and then crystallized to be a polycrystalline silicon layer. A first semiconductor layer 30 for a switching element “I” of a pixel portion, a second semiconductor layer 35 for an n-type switching element “II” of a driving portion and a third semiconductor layer 40 for a p-type switching element “III” of a driving portion are formed by patterning the polycrystalline silicon layer through a first mask process.
In FIGS. 3B and 4B, a gate insulating layer 45 of an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiO2) is formed on the first, second and third semiconductor layers 30, 35 and 40. First, second and third gate electrodes 50, 55 and 60 are formed on the gate insulating layer 45 by depositing and patterning a metallic material, such as molybdenum (Mo), through a second mask process. Then, the first, second and third semiconductor layers 30, 35 and 40 are doped with n-type impurities of a low concentration (n−) using the first, second and third gate electrodes 50, 55 and 60 as a doping mask. Accordingly, portions of each semiconductor layer 30, 35 and 40 directly under the corresponding gate electrode 50, 55 and 60 are not doped with impurities and remain intrinsic, and the other portions of each semiconductor layer 30, 35 and 40 are doped with n-type impurities of a low concentration (n−) to form LDD regions. The remaining intrinsic portions of each semiconductor layer 30, 35 and 40 function as an active region 30a, 35a and 40a for the switching elements.
In FIGS. 3C and 4C, first, second and third n+ photoresist (PR) patterns 62, 63 and 64 are formed on the first, second and third gate electrodes 50, 55 and 60 through a third mask process. Then, the entire surface of the substrate 20 is doped with n-type impurities of a high concentration (n+) using the first, second and third n+ PR patterns 62, 63 and 64 as a doping mask. The first n+ PR pattern 62 covers the first gate electrode 50 fully and portions of the first semiconductor layer 30 adjacent to the first gate electrode 50. Accordingly, the covered portions of the first semiconductor layer 30 are not doped with n-type impurities of a high concentration (n+) and remain as LDD regions, while the other portions of the first semiconductor layer 30 are doped with n-type impurities of a high concentration (n+). Similarly, since the second n+ PR pattern 63 covers the second gate electrode 55 fully and portions of the second semiconductor layer 35 adjacent to the second gate electrode 55, the covered portions of the second semiconductor layer 35 are not doped with n-type impurities of high concentration (n+) and remain as LDD regions, and the other portions of the second semiconductor layer 35 are doped with n-type impurities of a high concentration (n+). In addition, since the third n+ PR pattern 64 fully covers the third semiconductor layer 40, the third semiconductor layer 40 are not doped with n-type impurities of a high concentration (n+) and the LDD regions remain intact.
As a result, a first LDD region 30b and a first ohmic contact region 30c are obtained in the first semiconductor layer 30. Similarly, a second LDD region 35b and a second ohmic contact region 35c are obtained in the second semiconductor layer 35. After doping with n-type impurities, the first, second and third n+ PR patterns 62, 63 and 64 are removed.
In FIGS. 3D and 4D, first and second p+ PR patterns 65 and 66 are formed on the first and second gate electrodes 50 and 55, respectively, through a fourth mask process. Then, the entire surface of the substrate 20 is doped with p-type impurities of a high concentration (p+) using the first and second p+ PR patterns 65 and 66 as a doping mask. Since the first p+ PR pattern 65 completely covers the first semiconductor layer 30, the first semiconductor layer 30 is not doped with the high concentration of p-type impurities (p+). Similarly, since the second p+ PR pattern 66 completely covers the second semiconductor layer 35, the second semiconductor layer 35 is not doped with the high concentration p-type impurities (p+).
In contrast to the first and second semiconductor layers 30 and 35, since the third semiconductor layer 40 is exposed without any p+ PR pattern, the third semiconductor layer 40 is doped with the high concentration p-type impurities (p+). During the doping step of high concentration of p-type impurities, since the third gate electrode 60 shields the high concentration p-type impurities, a portion of the third semiconductor layer 40 directly under the third gate electrode 60 is not doped with the high concentration of p-type impurities and remains as an intrinsic active region 40a. In addition, the p-type impurities having a high concentration (p+) compensate the n-type impurities having a low concentration (n−). Accordingly, exposed portions of the third semiconductor layer 40 become a third ohmic contact region 40c doped with a high concentration p-type impurities. After doping with p-type impurities, the first and second p+ PR patterns 65 and 66 are removed.
In FIGS. 3E and 4E, an interlayer insulating layer 70 of an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiO2) is formed on the first, second and third gate electrodes 50, 55 and 60. The first, second and third sets of contact holes 73a, 73b, 75a, 75b, 77a and 77b are formed in the interlayer insulating layer 70 and the gate insulating layer 45 through a fifth mask process. The first set of contact holes 73a and 73b exposes the third ohmic contact region 30c. The second set of contact holes 75a and 75b and the third set of contact holes 77a and 77b expose the second ohmic contact region 35c and the third ohmic contact region 40c, respectively.
Next, after sequentially depositing molybdenum (Mo) and aluminum (Al) on the interlayer insulating layer 70, first source and drain electrodes 80a and 80b, second source and drain electrodes 83a and 83b, and third source and drain electrodes 87a and 87b are formed through a sixth mask process. The first source and drain electrodes 80a and 80b are connected to the first ohmic contact region 30c through the first set of contact holes 73a and 73b, respectively. The second source and drain electrodes 83a and 83b are connected to the second ohmic contact region 35c through the second set of contact holes 75a and 75b, respectively, and the third source and drain electrodes 87a and 87b are connected to the third ohmic contact region 40c through the third set of contact holes 77a and 77b, respectively.
In FIGS. 3F and 4F, after a passivation layer 90 of silicon nitride (SiNx) is formed on the first source and drain electrodes 80a and 80b, the second source and drain electrodes 83a and 83b, and the third source and drain electrodes 87a and 87b, a drain contact hole 95 exposing the first drain electrode 80b is formed in the passivation layer 90 through a seventh mask process. In addition, a pixel electrode 97 is formed on the passivation layer 90 by depositing and patterning an indium-tin-oxide (ITO) layer through an eighth mask process. The pixel electrode 97 is connected to the first drain electrode 80b through the drain contact hole 95.
Accordingly, a first switching element “I” of an n-type LDD polycrystalline silicon TFT is formed in the pixel portion, and a second switching element “II” of an n-type LDD polycrystalline silicon TFT and a third switching element “III” of a p-type polycrystalline silicon TFT are formed in the driving portion through eight mask processes. A mask process includes a coating step of PR, an exposure step and a developing step. Therefore, as the number of mask processes increases, production cost and fabrication time increases. Moreover, production yield is reduced because of the increased possibility of a malformation due to the large number of processes.